Low-power design of Reed-Solomon encoders

Reed-Solomon (RS) codes are one of the most widely used block error-correcting codes in modern communication and computer systems. Multiplication is the key computation in RS encoding. Adopting the generator polynomial with symmetric coefficients, the number of multipliers in RS encoders can be reduced by half, and their power consumption may also reduce. However, in some cases, the encoder based on the generator polynomial with asymmetric coefficients have better power performance. Additionally, since more than one primitive polynomial can generate a finite field with certain order, different choices of primitive polynomial also change the complexity of multipliers. In this paper, we exploited the relationship between the power consumption of RS encoders and their different encoding parameters. A simple way to find the encoder with the lowest power consumption is also presented. Simulation results prove its effectiveness.