An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity

We present a voltage domain implementation of a programmable delay axon circuit together with measurements from it. It was designed to be a building block for a polychronous spiking neural network. The axonal delay can be programmed by presenting an input spike followed by a post-synaptic spike at the desired delay. An analogue memory was used to store this value. We also use spike timing dependent delay plasticity (STDDP) to reduce the errors in delay that result from the delay programming step. Measurements show that the proposed circuit is capable of learning and retaining delays in the range of 2 ms to 50 ms for many minutes.