DocumentCode
626869
Title
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies
Author
Li Ding ; Jing Wang ; Zhangcai Huang ; Kurokawa, Akira ; Inoue, Yasuyuki
Author_Institution
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
fYear
2013
fDate
19-23 May 2013
Firstpage
1712
Lastpage
1715
Abstract
The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.
Keywords
CMOS logic circuits; integrated circuit modelling; logic gates; nanoelectronics; CMOS gate delay; SPICE simulation; multiple-input gates; nanometer technologies; overshooting effect; Analytical models; CMOS integrated circuits; Delays; Digital audio players; Logic gates; Semiconductor device modeling; Simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location
Beijing
ISSN
0271-4302
Print_ISBN
978-1-4673-5760-9
Type
conf
DOI
10.1109/ISCAS.2013.6572194
Filename
6572194
Link To Document