A multilevel fingerprinting method for FPGA IP protection

With the increasing risk of IP reuse in System on Chip (SoC) design, intellectual property (IP) techniques becomes one of the most important issues. Compare with watermarking, fingerprinting is a more effective method because is not only protects the IP owner´s benefits but also user´s rights. In this paper, we firstly propose a multilevel fingerprinting method for IP protection. In the typical field programmable gate array (FPGA) design flow, we first embed the watermarks into a FPGA design at netlist level by manipulating LUTs. When the IP core is compiled into a bitstream file, an individual fingerprint from IP user is then embedded into margin of FPGA. The experimental results show that the method has low resource and timing overhead, while proves a strong certificate both of IP owner and users.