A variable bandwidth amplifier for a dual-mode low-power ΔΣ modulator in cardiac pacemaker system

Author

Yeknami, Ali Fazli ; Alvandpour, Atila

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden

fYear

2013

fDate

19-23 May 2013

Firstpage

1918

Lastpage

1921

Abstract

This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.

Keywords

CMOS integrated circuits; amplifiers; cardiology; low-power electronics; modulators; pacemakers; CMOS; amplifier static power consumption; cardiac pacemaker system; consistent DC gain; dual-mode low-power Delta-Sigma modulator; frequency 0.9 MHz; frequency 1.7 MHz; frequency 2.3 MHz; gain 56 dB; power 180 nW; power 315 nW; programmable bandwidth amplifier; sensing-measuring stage; size 65 nm; supply voltage; tunable gain-bandwidth mode; ultralow-power biomedical implant; variable bandwidth amplifier; voltage 0.9 V; Bandwidth; CMOS integrated circuits; Capacitance; Gain; Modulation; Noise; Pacemakers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572242

Filename

6572242