DocumentCode :
626932
Title :
A novel energy-efficient serializer design method for gigascale systems
Author :
Kejun Wu ; Peng Liu ; Qiaoyan Yu
Author_Institution :
Dept. Inf. Sci. & Elec. Eng., Zhejiang Univ., Hangzhou, China
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
1978
Lastpage :
1981
Abstract :
Serial communication facilitates the high-speed communication in gigascale systems. Serializer designs typically use the current-mode logic to achieve high speed at the cost of large power consumption. For the latches in the serializer, the power-hungry current-mode logic is replaced with differential cascaded pass-gate to reduce the power and delay. For the selectors in the serializer, the conventional differential cascode voltage switch is modified with pass-gate logic by replacing a PMOS load with a resistor load and adding an inductive peaking structure. Simulation results show that the proposed method reduces the power-delay-product by up to 70%, compared to the conventional current-mode-logic-based serializer.
Keywords :
current-mode circuits; current-mode logic; delay circuits; flip-flops; logic circuits; resistors; switches; PMOS load; differential cascaded pass-gate logic; differential cascode voltage switch; energy-efficient serializer design method; gigascale system; high-speed serial communication; inductive peaking structure; latch; power consumption; power-delay-product; power-hungry current-mode logic; resistor load; Clocks; Delays; Latches; Logic gates; Power demand; Switches; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6572257
Filename :
6572257
Link To Document :
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