A 1.2V 10-bit 5 MS/s CMOS cyclic ADC

A 1.2V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This ADC design achieves DNL and INL of 0.32LSB and 0.42LSB respectively, while SNDR is 56.7 dB and SFDR is 67.8 dB at an input frequency of 400 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 3.6 mW in TSMC 0.18 m CMOS 1P6M process.