Low power quantizer design in CT Delta Sigma modulators

This paper presents the design of a 4 bit flash quantizer with an alternative low kickback, wide DC range input clocked core comparator. The quantizer is demonstrated within a third order continuous time (CT) ΔΣ modulator operating at an f_S of 1GHz with an OSR of only 10. In using the proposed clocked core and output latch, a reduction in current consumption within all preamplifiers and resistor ladder can be established. The schematic based flash quantizer is designed in a 1.2V supply 90nm TMSC process, consumes an overall 1.47 mW, and has a decision time of 132 ps. As demonstrating within the exemplary ΔΣ modulator, a coefficient dependent SNDR of 69.8 dB within a 50MHz bandwidth is achieved. When comparing to other state of the art ΔΣ modulator quantizers it achieves one of the lowest power consumptions.