A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs

A split-capacitor Vcm-based capacitor-switching scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) to reduce the capacitor-switching energy. By rearranging the structure and procedure of the capacitive array, the scheme can save the capacitor-switching energy by about 92% than the conventional scheme with better monotonicity. Meanwhile, a two-segment DC offset correction scheme for the comparator is also proposed to meet the speed and accuracy requirements. These techniques are utilized in the design of a 10b 70MS/s SAR ADC in 65nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2dB, while consuming 960μW from 1.2V supply. The figure of merit (FoM) is 36.8fJ/Conversion-step and the total active area is 220×220μm².