A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR

A 0.5V 6-to-10b rate-resolution scalable SAR ADC with microwatt power consumption is presented. Employing the successive approximation register (SAR) architecture, the proposed ADC exhibits the sampling rates of 125kS/s, 150kS/s and 250kS/s at scalable resolutions of 10b, 8b and 6b, respectively. A low-leakage voltage boosting technique is proposed, which reduces the leakage of MOS switches by 99% as compared to conventional techniques. This has ensured the ADC operating at sampling rates from 175kS/s to 5kS/s with only 0.2b ENOB degradation. Meanwhile, the effect of bridge capacitor on the linearity of merged capacitor switching (MCS) DAC is discussed. Demonstrated in a 0.13μm CMOS process, measured results show the ADC achieves ENOB of 8.51b, 7.42b, and 5.97b at 10b, 8b, and 6b modes, respectively. At 10b 125kS/s, the entire ADC consumes only 3.4μW from a 0.5V supply.