A 1.5-bit/stage pipeline ADC with FFT-based calibration method

A fast Fourier transform-based (FFT-based) foreground digital calibration method for multistage pipeline analog-to-digital converter (ADC) is proposed in this paper. The calibration method can overcome the capacitor mismatch and finite gain of the operational amplifier (OPAMP). Given that the capacitor mismatch and finite OPAMP gain cause the radix of all the stages of multistage pipeline ADC to become unequal to 2ⁿ, the FFT processor can be adopted to evaluate the real radixes of all the stages and generate new digital output to compensate the error caused by these nonideal effects. Moreover, because capacitor mismatch and the finite gain of OPAMP can be compensated, low-gain OPAMP can be used in high-performance ADC to reduce the power dissipation, and the small capacitor can be adopted to save the area. An example of a 10-bit 1.5-bit/stage pipelined ADC with only an 8-bit circuit performance is implemented in 0.18 μm TSMC CMOS process. The circuit measurement result reveals that the signal-to-noise-and-distortion ratio (SNDR) of 51.03 dB with 11-dB improvement after calibration can be achieved at the sample rate of 1 MHz.