Title :
A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology
Author :
Chua-Chin Wang ; Wen-Je Lu ; Hsin-Yuan Tseng
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A high-speed compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 40 nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load, the maximum slew rate is 0.53 (V/ns), and the core area of the proposed design is 0.052 × 0.254 mm2.
Keywords :
CMOS integrated circuits; buffer circuits; compensation; detector circuits; electric sensing devices; elemental semiconductors; integrated circuit design; integrated circuit measurement; silicon; CMOS technology; PVT detection; Si; capacitance 20 pF; frequency 460 MHz; frequency 500 MHz; high-speed 2xVDD output buffer; high-speed compensation technique; output driving current; process-voltage-σtemperature detection; size 40 nm; slew rate adjustment; slew rate compensation performance; voltage 0.9 V; voltage 1.8 V; CMOS integrated circuits; CMOS process; MOS devices; Temperature sensors; Threshold voltage; Voltage measurement; I/O buffer; PVT variation; floating N-well circuit; gateoxide reliability; mixed-voltage tolerant; slew rate compensation; threshold voltage detection;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572283
