Delay-variation-tolerant FIR filter architectures based on the Residue Number System

This paper investigates the use of the Residue Number System (RNS) in the hardware design of VLSI FIR filters implemented in nano-scale technologies prone to process variation effects. It is here shown that the RNS substantially reduces the filter sensitivity to delay variations, when compared to digital filter designs that use conventional positional number systems, such as the widely-used two´s-complement representation. The inherent tolerance of the introduced RNS architectures to the delay variations, is here shown to allow to circumvent the use of large design parameter margins. Therefore, we demonstrate that the use of RNS can achieve a high timing yield without resorting to costly over-design, which may unnecessarily increase system complexity. The particular benefit comes in addition to area, time and power benefits achieved due to the use of the RNS. The quantitative digital filter design space exploration reported in the paper takes into consideration the filter order as well as criteria related to the filter output signal quality such as the signal-to-noise ratio (SNR) and it demonstrates that the proposed architectures offer effective solutions for hardware design using modern and future nano-scale processes, for filter cases of practical interest.