A SAR ADC with energy-efficient DAC and tri-level switching scheme

This paper presents a 10-bit successive approximation register (SAR) ADC with an energy-efficient switching approach of capacitive DAC. The proposed switching method lessens the dynamic offset effect coming from the asymmetric capacitive switching. A tri-level algorithm is applied additionally to make the ADC more power-efficient and is implemented with switching-capacitive voltage generator without consuming static power. It consumes 3.87μW at 0.5V supply and 1.28MS/s sampling rate, and achieves ENOB of 9.69-bit and FOM of 3.66 fJ/conversion-step. This SAR ADC has been fabricated by TSMC 90nm CMOS process technology.