A high resolution FPGA-based merged delay line TDC with nonlinearity calibration

This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 50 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 16.6% and 5.4% as compared with traditional one, respectively. Furthermore, 29 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.