A 14-bit pipelined ADC with digital background nonlinearity calibration

A digital background calibration algorithm is proposed to overcome nonlinearity caused by finite opamp gain and capacitor mismatch in pipelined analog-to-digital converter (ADC). The scheme, code frequency statistics (CFS), does not modify the classic pipelined stage, needs none of extra testing signals, and reduces the linearity requirement of the analog circuit. CFS is suitable for generic input and the cost of hardware is low. An experimental 14-bit pipelined ADC is fabricated to verify CFS. At 15MS/s, the measurement results show that INL errors drop from 90LSB to 0.8 LSB, SNDR grows from 38.6 dB to 66.7 dB, THD drops from -37.3dB to -82.8dB, and SFDR grows from 41.6 dBc to 86.1 dBc. The linearity of the pipelined ADC is improved significantly.