Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing

This paper presents a flow composed by a set of heuristic algorithms to address the discrete gate sizing and Vt assignment problem for leakage power minimization while satisfying delay, load and slew constraints. The proposed flow combines the Fanout-of-4 empirical rule, the Logical Effort concept, a Simulated Annealing (SA) as the main engine, as well as a new set of specific optimization strategies to solve this difficult problem as formulated in the 2012 ISPD Gate Sizing Contest. The main contribution of this work is to show how a sequence of Simulated Annealing runs, starting from a solution given by Logical Effort, Fanout of-4 rule, and employing a set of new techniques can be used together to solve gate sizing problems of up to a million gates. New methods are presented to solve violations during the Annealing and a dynamic cost function is presented that helps SA to achieve different conflicting tasks during the optimization. The entire flow was able to achieve the second and first ranks in the ISPD 2012 Contest. A set of different experiments is presented to support design decisions and highlight the quality of the achieved results.