Analytic modeling of interconnect capacitance in submicron and nanometer technologies

Parasitic capacitance of interconnects in the analog and mixed-signal VLSI circuits can be modeled by using physics equations or empirical curve fitting. In this paper, we propose an analytical model for computing parasitic capacitance between interconnects on different layers or on the same layer. In our method, electric flux is approximated to model different capacitive components, which combine to determine the overall equivalent capacitance. We first derive a general template for the fringe capacitance based on fundamental electromagnetic principles, followed by a fitting technique in order to reach outstanding accuracy. Based on our approach that includes no complex operators, capacitance of typical interconnect geometries can be efficiently computed. The proposed model is verified in comparison with the extracted results derived from commercial tools. The experimental results show that our proposed method can best approach the extracted results yet with significantly reduced computation time.