DPA resistance of charge-sharing symmetric adiabatic logic

We investigate our previously proposed charge sharing symmetric adiabatic logic, which was designed to thwart differential power analysis (DPA) attack. The ability of the logic to withstand DPA attacks is analyzed from the variations in the transitional power consumption of individual logics and in the bit-parallel cellular multiplier over GF(2^m). Then, we compare the results with those of the previous secure logic styles using the same parameters and under the same conditions. Based on the simulated program with integrated circuit emphasis (SPICE) simulation results, we deduce that our proposed logic is a suitable candidate for secure hardware application in the low-power and low-frequency fields, such as contactless smart card, RFID tags, and wireless sensors.