A low power all-digital self-calibrated temperature sensor using 65nm FPGAs

This paper presents an all-digital self-calibrated delay-line based temperature sensor. A continuous self-calibration technique is proposed to remove process variations and to generate direct digital representations of temperature. A power saving scheme using a hybrid counter/pulse position decoder is also introduced without any increase in area overhead. Four different architectures including traditional long and short delay-lines, and the proposed power saving hybrid sensor with long and short delay-lines are implemented on multiple 65nm Cyclone III FPGAs along with an on-chip continuous self-calibration circuit. The logic utilization for a single sensor is as small as 60 Logic Elements (LE) and its measured power consumption is as low as 2.9 μW, with errors less than ±1.6°C from 20°C to 75°C.