Synthesis of 3D clock tree with pre-bond testability

Three-dimensional integrated circuits (3D-ICs) is a promising way to implement system-on-chip. To achieve acceptable manufacturing yield, pre-bond test is necessary to make sure only good dies are bonded. A true 3D clock tree requires shorter overall routing lengths and consumes lower power. However, a true 3D clock tree also renders pre-bond test impossible since there are not complete clock trees in dies under test. Therefore, redundant trees have to be added to make dies pre-bond testable. In this paper, we propose a heuristic approach for 3D clock tree synthesis targeted to minimize the number of Through-Silicon-Vias (TSV) and reduce the overhead for redundant trees. Experimental results show that the proposed method can achieve both goals efficiently.