Title :
Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance
Author :
Hong Zhu ; Kursun, V.
Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
Abstract :
Switching speed, power consumption, standby leakage current, and silicon area are major concerns in buffer design. A novel dual-threshold-voltage buffer is proposed in this paper for higher energy efficiency and shorter propagation delay while driving high capacitive load. The novel buffer offers up to 23.3% shorter propagation delay, 13.6% less switching energy consumption, and 75.7% lower standby leakage current as compared to the conventional drivers under equal silicon area and identical extrinsic load capacitance conditions in a TSMC 65nm multi-threshold-voltage CMOS technology.
Keywords :
CMOS integrated circuits; buffer circuits; invertors; leakage currents; buffer design; capacitive load; dual-threshold-voltage buffer; dual-threshold-voltage energy-efficient buffer; energy consumption; energy efficiency; extrinsic load capacitance; multithreshold-voltage CMOS technology; power consumption; propagation delay; silicon area; size 65 nm; standby leakage current; switching speed; CMOS integrated circuits; Capacitance; Inverters; Leakage currents; MOSFET; Propagation delay; battery lifetime; dual-threshold voltages; energy efficiency; leakage current; propagation delay; tapered buffer;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572510
