Energy reduction of ultra-low voltage VLSI circuits by digit-serial architectures

Ultra-low voltage VLSI designs are gaining widespread attention due to the requirements of minimum energy consuming motes. Leakage energy is a considerable part of the overall energy consumed in the ultra-low voltage domain. This paper deals with the overall energy reduction in ultra-low power systems by the use of digit-serial implementations. Leakage energy is reduced by the reduction of hardware in digit-serial implementations. However, overhead circuitry adds to the energy budget. It has been shown in this paper that digit-serial implementations do reduce the overall energy consumption in the ultra-low power VLSI circuits compared to bit-serial and wordparallel implementations. 73% and 92% reduction in energy per clock cycle was obtained with an 8-bit adder at a source voltage of 0.7V compared to the bit-serial and word-parallel implementations respectively.