Scalable low power digital filter architectures for varying input dynamic range

Architecture level optimizations for reducing power consumption in commonly used digital filter implementations are studied. We look at two optimizations (data shifting and offset addition) when the operating condition is very different from the worst case scenarios for which the filters are designed, and show how to use them to exploit this behavior. We study the reduction in switching activity for different input conditions. The power consumption of the proposed architectures are compared against reference designs using prelayout synthesis netlist with a 45 nm CMOS library and the results are tabulated.