Balancing Adder for error tolerant applications

Recent imprecise hardware (IHW) design methodologies present opportunities for achieving gains in nonfunctional efficiency design metrics by allowing errors in computation within error tolerant application domains. This work presents a novel imprecise Error Tolerant Balancing Adder (ETBA) design - an augmentation of the ETAIIM IHW adder that reduces errors by introducing a balance block that detects and corrects carry chain inconsistencies in the ETAIIM but operates off the critical path. Furthermore, this work identifies a common class of killer inputs with high error rates for IHW adders, and demonstrates the ETBA´s resilience to these errors. A JPEG decompression case study reveals a 24% reduction in ETBA addition energy-delay product compared to a Kogge-Stone adder with only a 0.2% reduction in SSIM image quality.