• DocumentCode
    627217
  • Title

    Study of threshold voltage of p-channel four gate transistor

  • Author

    Noor, Samantha Lubaba ; Haq, A. F. M. Saniul ; Hassan, Mehdi

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
  • fYear
    2013
  • fDate
    17-18 May 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A three dimensional model of SOI p-channel four gate transistor has been developed using device simulator Silvaco/ATLAS. Threshold voltage for the device is studied for different biasing condition at the four gates and different physical parameter like channel length. The results are compared to the results obtained from the analytical model of threshold voltage of n-channel four gate transistor to find out whether the analytical model works for p-channel G4-FET also.
  • Keywords
    MOSFET; silicon-on-insulator; SOI p-channel four gate transistor three dimensional model; Silvaco-ATLAS device simulator; n-channel gate transistor threshold voltage; p-channel G4-FET; p-channel four gate transistor threshold voltage; Analytical models; Electric potential; Junctions; Logic gates; Numerical models; Threshold voltage; Transistors; Four Gate Transistor; Fully Depleted; SOI; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Informatics, Electronics & Vision (ICIEV), 2013 International Conference on
  • Conference_Location
    Dhaka
  • Print_ISBN
    978-1-4799-0397-9
  • Type

    conf

  • DOI
    10.1109/ICIEV.2013.6572568
  • Filename
    6572568
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=627217