VLSI floorplanning design using clonal selection algorithm

Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. It is an important step of VLSI design methodology. It gives answer to the different question of VLSI design such as shape of modules, location of modules etc. The floorplanning problem aims to arrange a set of rectangular modules on a rectangular chip area so as to optimize an appropriate measure of performance. This problem is known to be NP-hard, and is particularly challenging if the chip dimensions are fixed. A Clonal Selection Algorithm for a slicing and hard-module VLSI floorplanning problem is presented. The Clonal Selection Algorithm has been implemented and tested on popular MCNC and GSRC benchmarks. Experimental results show that the Clonal Selection Algorithm can produce optimal or nearly optimal solutions for all the benchmark problems. We present a Clonal Selection Algorithm which used an O-tree representation for VLSI floorplanning representation.