Title :
Signal integrity characterization of high-speed I/O in 3D chip-package system
Author :
Hyunho Baek ; Eisenstadt, William R.
Author_Institution :
Dept. Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
Abstract :
This paper presents signal integrity characterization of 3D TSVs and interconnect using high-speed I/O in a 3D chip-package system. The authors designed and fabricated a Gunning Transceiver Logic (GTL) I/O Test IC using Tezzaron 3D CMOS 150um technology. The test IC has two different tiers which are labeled top and bottom. GTL I/O is placed on each tier to evaluate the TSV and interconnect signal integrity characterization with IGbps data signals. In order to characterize the interconnect in chip-package system, the test ICs were ball-bonded on to a custom FR-4 board designed for measuring high speed transients. Comparison measurements between on-chip and off-chip signals were performed. Also, the GTL I/O drivers switching was enabled at different tiers with a control signal. In addition, specific data patterns are utilized to characterize lSI (Inter-Symbol Interference) from different tiers.
Keywords :
CMOS integrated circuits; chip scale packaging; integrated circuit interconnections; intersymbol interference; three-dimensional integrated circuits; transients; 3D TSV; 3D chip-package system; FR-4 board; GTL I/O Test IC; Gunning Transceiver Logic; IGbps data signals; high speed transients; high-speed I/O; inter-symbol interference; interconnect; lSI; off-chip signals; signal integrity characterization; size 150 mum; CMOS integrated circuits; Gain measurement; Jitter; Semiconductor device measurement; Switches; Through-silicon vias; 3D Technology; FR-4 board; High-Speed I/O; Interconnect; Signal Integrity; TSV; Tezzaron;
Conference_Titel :
Wireless and Microwave Technology Conference (WAMICON), 2013 IEEE 14th Annual
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4673-5536-0
Electronic_ISBN :
978-1-4673-5535-3
DOI :
10.1109/WAMICON.2013.6572738
