A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS

We propose a time-to-digital converter (TDC) that uses a G_m-C integrator to translate the time interval into voltage, and quantizes this voltage with a SAR-ADC. The proposed method is capable of achieving pico-second resolution, avoiding limitations in delay-chain-based TDCs, such as limited resolution to the buffer delay, mismatches, and voltage surge. Furthermore, taking the advantages of SAR-ADC, small area and low power consumption of voltage quantization are attainable. The chip was fabricated in 90nm CMOS. Its measured DNL and INL are -0.6/0.7 LSB and -1.1/2.3 LSB, respectively, with 1ps per LSB in a 9-bit range.