A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation

This study proposes a floorplan method for asynchronous circuits with bundled-data implementation to support ASIC designs. The proposed method based on Simulated Annealing (SA) and sequence-pair minimizes both latency and chip size of bundled-data Implementation considering setup constraints. In the experiments, the floorplan results obtained by the proposed method are evaluated in terms of latency and chip size by changing parameters of SA and weights for latency and chip size.