A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

A 128 Mb 0.07 μm² 6T high-density SRAM bitcell with write-assist circuitry has been successfully implemented using 16 nm high-k metal gate FinFET technology. This study proposes two write-assist techniques: 1) suppressed coupling signal negative bit-line (SCS-NBL) technique and 2) write recovery enhanced lower cell-VDD (WRE-LCV) technique to reduce the SRAM minimal supply voltage. The area overheads of these two techniques are 2% and 3%, respectively. The silicon data show that both of these techniques can improve overall SRAM VMIN performance by more than 300 mV at the 95th percentile.