Two-level hierarchical fill-buffer for graphics rendering systems

Optimization of buffer access is one of the critical design issues of graphics rendering systems especially for embedded applications where the memory bandwidth is very limited. This paper presents an efficient hierarchical fill-buffer architecture for two-dimensional (2D) graphics rendering systems. The fill-buffer is used to determine the interior regions of graphics objects and consumes considerable memory bandwidth during the rendering process. By using an additional level of auxiliary buffer to denote the status of blocks of fill-buffer entries, the proposed method cannot only clear the fill-buffer efficiently with much less cycles and data transfer, but also accelerate the winding-count accumulation process significantly. Our experimental results show that the number of data accesses can be reduced by more than a factor of 3. If the auxiliary buffer is placed on-chip, the off-chip memory bandwidth can be reduced by more than a factor of 10. The other salient feature of the proposed fill-buffer is that it can be integrated with the depth buffer used in three-dimensional (3D) graphics in order to reduce the overall cost by sharing the same buffer circuits.