• DocumentCode
    627774
  • Title

    Adaptive zero-crossing digital phase-locked loop for packet synchronization

  • Author

    Al-Araji, Saleh R. ; Salahat, Ehab ; Kilani, Dima ; Yasin, Shahd Abu ; Alkhoja, Heba ; Aweya, James

  • Author_Institution
    Dept. of Electr. Eng., Khalifa Univ., Sharjah, United Arab Emirates
  • fYear
    2013
  • fDate
    16-19 June 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.
  • Keywords
    digital phase locked loops; finite state machines; packet radio networks; synchronisation; AZC-DPLL; FSM; adaptive zero-crossing digital phase-locked loop; finite state machine; frequency recovery; frequency synchronization; packet network; packet synchronization; raised cosine pulse shaping; Adaptive systems; Digital filters; Frequency synchronization; Phase locked loops; Pulse shaping methods; Reliability; Synchronization; Digital Phase-locked Loops; Packet Network; Raised Cosine Pulse Shaping; Synchronization; Zero crossing Digital Phase lock loops;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4799-0618-5
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2013.6573607
  • Filename
    6573607