A VCO linearization system for ADC applications

Author

Michaelsen, J.A. ; Wisland, D.T.

Author_Institution

Nanoelectron. Group Dept. of Inf., Univ. of Oslo, Oslo, Norway

fYear

2013

fDate

16-19 June 2013

Firstpage

1

Lastpage

4

Abstract

Time-domain ADCs are increasing in popularity due in part to compatibility with deep sub-micron (DSM) CMOS technology. The performance of time-domain ADCs that use VCOs in open loop is to a large extent limited by the linearity of the output frequency of the VCO as a function of its control voltage. In this paper, we present an analysis of a system for VCO linearization, suppressing distortion and phase noise introduced by the VCO. We connect the noise from each component of the system to the performance of the ADC. Further, we demonstrate the feasibility of the system with transistor level simulations. We designed the simulated system for 12 bit linearity and simulated the transistor level model using a commercially available 90 nm CMOS process design kit (PDK).

Keywords

CMOS integrated circuits; analogue-digital conversion; time-domain analysis; voltage-controlled oscillators; CMOS process design kit; DSM technology; PDK; VCO linearization system; analogue-digital conversion; control voltage; deep submicron technology; distortion suppression; open loop; phase noise suppression; size 90 nm; time-domain ADC; transistor level simulations; voltage-controlled oscillators; word length 12 bit; Linearity; Phase noise; Transfer functions; Transient analysis; Transistors; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International

Conference_Location

Paris

Print_ISBN

978-1-4799-0618-5

Type

conf

DOI

10.1109/NEWCAS.2013.6573623

Filename

6573623