Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains

On-going advancements in 3D manufacturing are enabling 3D ICs to contain several processing cores, hardware accelerators and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard IPs. Thus, as diverse and heterogeneous circuits can be implemented on a 3D IC, it also leads to use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3D potentials, they also introduce power delivery challenges. This work discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3D global power delivery network (PDN). We first present power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. Experiments show that TSVs contribute to power supply noise and heat sharing among tiers.