A netlist pruning tool for an electronic system prototyping platform

Author

Baratli, Karim ; Lakhssassi, Ahmed ; Blaquiere, Yves ; Savaria, Yvon

Author_Institution

U. du Quebec en Outaouais, Gatineau, QC, Canada

fYear

2013

fDate

16-19 June 2013

Firstpage

1

Lastpage

4

Abstract

The increasing complexity of electronic systems makes the recognition of subcircuits in a main circuit a desirable feature to several Electronic Design Automation tools (EDA). This paper presents an efficient Netlist Pruning Tool (NPT) for an electronic system prototyping platform. The tool first parses any EDIF netlist and represents the circuit into a graph. Then a subgraph isomorphism algorithm is applied for detecting the subcircuits´ patterns and, for each pattern detected, appropriate actions are triggered. NPT was successfully applied to several PCB netlists to prune typical pull-up/pull-down resistors and decoupling capacitors, such as a netlist with up to 51 233 components and 70354 nets with a run time of 101.32 s.

Keywords

capacitors; electronic design automation; graph theory; printed circuits; resistors; EDA; EDIF netlist; NPT; PCB netlist; decoupling capacitor; electronic design automation tool; electronic system prototyping platform; netlist pruning tool; pull-down resistor; pull-up resistor; subcircuit pattern detection; subcircuit recognition; subgraph isomorphism algorithm; time 101.32 s; Algorithm design and analysis; Capacitors; Conferences; Design automation; Integrated circuits; Pattern recognition; Resistors; CAD; EDA; EDIF; Filtering; IC; Netlist; Pruning; isomorphism; pattern; subgraph;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International

Conference_Location

Paris

Print_ISBN

978-1-4799-0618-5

Type

conf

DOI

10.1109/NEWCAS.2013.6573647

Filename

6573647