A netlist pruning tool for an electronic system prototyping platform

The increasing complexity of electronic systems makes the recognition of subcircuits in a main circuit a desirable feature to several Electronic Design Automation tools (EDA). This paper presents an efficient Netlist Pruning Tool (NPT) for an electronic system prototyping platform. The tool first parses any EDIF netlist and represents the circuit into a graph. Then a subgraph isomorphism algorithm is applied for detecting the subcircuits´ patterns and, for each pattern detected, appropriate actions are triggered. NPT was successfully applied to several PCB netlists to prune typical pull-up/pull-down resistors and decoupling capacitors, such as a netlist with up to 51 233 components and 70354 nets with a run time of 101.32 s.