A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts

Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub-micron region. In order to manufacture ICs with high quality, methodology and analysis must include reliability consideration in design loop. In this paper, we propose a new statistical reliability-aware approach to evaluate circuit performance under ageing effects and process variations. BSIM4 transistor physical parameters are investigated. The non-dominated sorting-based multi-objective evolutionary algorithms is used to find the worst-case aged circuit performances. This approach is studied with a two stage Miller-operational-amplifier (Op-Amp) with 65nm CMOS technology. Simulation results show that the Op-Amp is HCI non-sensitive but suffer from NBTI degradation. Compared to traditional Monte-Carlo method, simulation time is reduced to 40%, with a trade-off of only 0.05% to 1.7% accuracy loss.