DocumentCode :
627829
Title :
Controlled start-up stochastic decoding of LDPC codes
Author :
Maamoun, M. ; Bradai, Rafik ; Naderi, Ali ; Beguenane, R. ; Sawan, Mohamad
Author_Institution :
Dept. of Electron., Univ. of Blida, Blida, Algeria
fYear :
2013
fDate :
16-19 June 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper concerns a new and powerful Low-Density Parity-Check (LDPC) stochastic decoding algorithm, called Controlled Start-up Stochastic (CSS) decoding, to implement fully parallel LDPC decoders. The proposed algorithm uses a clever starting point computing method to improve the convergence as well as to reduce the latency of the decoding process, without a significant hardware complexity cost. Using this stochastic method, in low signal-to-noise ratio (SNR) region, a short LDPC code can outperforms the fixed point state-of-the-art (2048, 1723) LDPC code. To validate the performance of the proposed algorithm, a (48, 24) LDPC code are implemented on Xilinx Virtex-6 VLX240T field programmable gate array device, with and without the CSS method. The new algorithm provides a decoding speed seven times faster and a Bit Error Rate (BER) hundred times better at E3/N0=4.5 dB. In addition, the results provide a BER better than the 6 bits offset min-sum algorithm (OMSA) and better than the 6 bits sum-product algorithm (SPA) for the (2048, 1723) LDPC code, below E3/N0=3.9 dB and Eb/N0=4.3 dB respectively. The obtained results show that, the proposed algorithm is the first stochastic algorithm which can outperform the OMSA and SPA algorithms, with less hardware complexity.
Keywords :
codecs; decoding; error statistics; field programmable gate arrays; parity check codes; BER; LDPC codes; OMSA; SPA algorithms; Xilinx Virtex-6 VLX240T field programmable gate array device; bit error rate; controlled start-up stochastic decoding; fully parallel LDPC decoders; hardware complexity; low-density parity-check; offset min-sum algorithm; signal-to-noise ratio; stochastic algorithm; stochastic decoding algorithm; sum-product algorithm; Bit error rate; Cascading style sheets; Decoding; Hardware; Iterative decoding; Signal to noise ratio; Controlled start-up stochastic decoding; field programmable gate array (FPGA); iterative decoding; low-density parity-check code;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International
Conference_Location :
Paris
Print_ISBN :
978-1-4799-0618-5
Type :
conf
DOI :
10.1109/NEWCAS.2013.6573662
Filename :
6573662
Link To Document :
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