DocumentCode
627834
Title
A 0.9 V low-power reconfigurable successive approximation ADC for integrated sensors
Author
Zhang, Enxia ; Mawelo, Roger Mvika ; Fayomi, Christian ; Nabki, Frederic
Author_Institution
CoFaMic Res. Centre, Univ. du Quebec a Montreal Montreal, Montreal, QC, Canada
fYear
2013
fDate
16-19 June 2013
Firstpage
1
Lastpage
4
Abstract
In this paper, a reconfigurable successive approximation analog-to-digital converter with selectable resolutions ranging from 7 to 10 bits is presented. The circuit is implemented in IBM CMOS 0.13 μm technology, and operates with a 0.9 V supply. The simulated effective number of bits (ENOB) ranges from 6.66 to 9.75, while the simulated power consumption during a continuous conversion ranges from 194 nW (7 bits) to 418 nW (10 bits) at a sampling rate of 50 kS/s.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; microsensors; analog-to-digital converter; integrated sensors; low-power reconfigurable successive approximation ADC; power 194 nW; power 418 nW; size 0.13 mum; voltage 0.9 V; Approximation methods; Capacitors; Clocks; Power demand; Registers; Sensors; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International
Conference_Location
Paris
Print_ISBN
978-1-4799-0618-5
Type
conf
DOI
10.1109/NEWCAS.2013.6573667
Filename
6573667
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