Analysis and optimization of buffer circuits in high current gate drives

Buffer circuits are widely used in high-power inverters´ gate drives to get enough driving current for power modules or power transistors in parallel. In this paper, designs of buffer circuits to boost the output current for a gate driver IC are investigated. Different buffer topologies are reviewed and their individual advantages and disadvantages analyzed. Based on the analysis, three topologies, specifically the BJT emitter follower, the two NFETs totem pole, and the CMOS buffer, are chosen for further study. Optimizations are performed on these three buffers by taking the driving capability, switching speed, circuit complexity, and cost into account. After that, a test setup is built, and the driving performance of the buffers is characterized and then compared experimentally with a commercial buffer IC with a rated current of 30 A. All three proposed buffers show better performance and lower cost, which verifies the feasibility and effectiveness of the proposed optimization methods. Double pulse test results indicate that the addition of a buffer stage makes the switching performance less sensitive to the load and can achieve significant performance improvement when large or parallel power switches are to be driven.