3D Integration technologies using self-assembly and electrostatic temporary multichip bonding

Author

Fukushima, Tetsuya ; Hashiguchi, Hironori ; Bea, Jichel ; Murugesan, Mariappan ; Lee, Ki-Won ; Tanaka, T. ; Koyanagi, Mitsumasa

Author_Institution

New Ind. Creation Hatchery Center (NICHe), Tohoku Univ., Sendai, Japan

fYear

2013

fDate

28-31 May 2013

Firstpage

58

Lastpage

63

Abstract

We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 μm was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and then formed through-silicon vias (TSVs) for the self-assembled KGDs to fabricate 3D-stacked chips with Cu-TSVs and Cu/SnAg microbumps. By using the new multichip-to-wafer 3D integration process with SAE bonding, we obtained good electrical characteristics from the self-assembled KGDs having Cu-TSVs and Cu/SnAg microbumps.

Keywords

copper; integrated circuit bonding; self-assembly; silver alloys; three-dimensional integrated circuits; tin alloys; 3D-stacked chips; Cu-SnAg; SAE bonding technique; chip-to-wafer 3D integration technology; electrical characteristics; electrostatic bonding force; electrostatic temporary multichip bonding; high-throughput multichip self-assembly; multichip transfer processes; multichip-to-wafer 3D integration process; self-assembled known good dies; through-silicon vias; Accuracy; Bonding; Dielectrics; Electrodes; Electrostatics; Self-assembly; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Conference_Location

Las Vegas, NV

ISSN

0569-5503

Print_ISBN

978-1-4799-0233-0

Type

conf

DOI

10.1109/ECTC.2013.6575550

Filename

6575550