A novel non-TSV approach to enhancing the bandwidth in 3-D packages for processor-memory modules

We describe here an alternative 3-D chip stacking technology under development at APSTL that delivers the performance enhancement possible with TSVs (e, g. bandwidth of 12.8 GB/sec, specific I/O power consumption reduced by 10× to 100 mW/GB/sec) without having to create TSVs in the functional chips themselvesA. The resulting module can be tested/packaged into conventional 3-D packages e.g. PiP or PoP using technologies in place at OSATs. This feat has been achieved by adding low-cost compensatory features to individual interconnect lines which allow raising the clock rate even in conventional packages. Simulation results will be presented to establish that up to a I/O clock rate of 800 MHz (2× current in SmartPhones & Tablets) the output from this new low - cost package is identical to that from TSV modules. Physical package design and test/assembly sequences will be discussed. With this novel approach that leverages only current technologies to improve inter - chip bandwidth and power consumption, performance limits of existing 3-D stacked packages e, g. PoP and PiP have been removed and these established low-cost packages have been made competitive with 3D - TSV packages for several future generations of chips intended for SmartPhones & Tablets.