• DocumentCode
    628370
  • Title

    Three-path electroplated copper compliant interconnects — Fabrication and modeling studies

  • Author

    Okereke, Raphael ; Sitaraman, Suresh K.

  • Author_Institution
    George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2013
  • fDate
    28-31 May 2013
  • Firstpage
    129
  • Lastpage
    135
  • Abstract
    Compliant interconnects have been studied in universities and industry over the past decade, as compliant interconnects could mechanically decouple the die from the substrate and thus could reduce the stresses in the die. In this work, we present the design, fabrication and modeling results of three-path electroplated compliant interconnect that addresses several of the challenges associated with various other compliant interconnects. Sample interconnects were fabricated on 4" wafers to enable experimental validation of the designed microstructures. There were about 8300 interconnects on each 20 × 20 mm2 chip in area-array layout. The interconnects were subjected to compliance testing. In parallel to the experiments, finite-element simulations were carried out to determine the mechanical compliance and the electrical resistance of the interconnects as well as their thermo-mechanical reliability. It is seen that the out-of-plane mechanical compliance will be more than 1 mm/N, several orders of magnitude greater than solder bump interconnects, and from a reliability perspective, the interconnects will last at least 1000 thermal cycles.
  • Keywords
    circuit layout; circuit reliability; circuit testing; copper; electroplating; finite element analysis; interconnections; network synthesis; solders; Cu; compliance testing; electrical resistance; finite-element simulation; mechanical die decoupling; microstructure design; out-of-plane mechanical compliance; solder bump interconnection; thermomechanical reliability; three-path electroplated copper compliant interconnection; wafer; Assembly; Fabrication; Finite element analysis; Inductance; Resistance; Stress; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
  • Conference_Location
    Las Vegas, NV
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4799-0233-0
  • Type

    conf

  • DOI
    10.1109/ECTC.2013.6575562
  • Filename
    6575562