Reliability study for large silicon interposers report on board

This paper presents a reliability study on a 15×15mm² silicon interposer packages, 5 times larger surface than usual studies on wafer level chip scale package (WLCSP). Works were conducted in the frame of silicon platform developments for heterogeneous RF 3D modules, where the interconnections number is lower than in digital applications but the silicon interposer larger than conventional WLCSP. Several key parameters for Thermal Cycles on Board (TCoB) and Drop Test (DT) performances have been evaluated: ball type (standard SAC ball (stdb), polymer core solder balls (PCSB)), first and second passivation layers (mineral, polymers: ALX, PBO), die size (5×5, 10×10, 15×15 mm²), ball layout (full and partial matrix) and ball location (corner, main matrix). A 4-masks type test vehicle comprising copper routing, passivation and under bump metallization levels has been designed. The pitch is 800μm and the die thickness is 400μm. Different configurations have been manufactured and balled at wafer level. Reliability trials have been carried out following JEDEC recommendations for board design, TCoB and DT. Usual conditions for mobile applications have been used for reliability tests (-40°C/+125°C, 2 cycles per hour, and 1500g drops, 0.5ms half pulse duration) with continuous monitoring. With PCSB and ALX passivation, characteristic life was obtained above 300 drops and around 450 thermal cycles. Skipping balls in corner, TCoB first failure above 500 cycles is achieved with double polymer passivation and standard SAC balls. Finite element modelling is also presented to highlight the stressed areas in the different tested structures. For each factor of this extensive study, Weibull plot lifetime statistics and fracture mode analyses have been conducted, leading to a few guidelines in terms of layout, materials and structures for compliant interconnections of future large 2.5D and 3D silicon i- terposers reported on board.