• DocumentCode
    628439
  • Title

    Dielectric stack engineering for via-reveal passivation

  • Author

    Crook, Kath ; Carruthers, Mark ; Archard, Daniel ; Burgess, Simon ; Buchanan, Kris

  • Author_Institution
    SPTS Technol., Newport, UK
  • fYear
    2013
  • fDate
    28-31 May 2013
  • Firstpage
    576
  • Lastpage
    580
  • Abstract
    This paper reports on the development of low temperature (<;190°C) plasma-enhanced chemical vapour deposition (PECVD) processes used to deposit dielectric films for use as passivation layers over wafer back side revealed vias in thinned (<;60μm), 300mm silicon wafers.
  • Keywords
    dielectric thin films; passivation; plasma CVD; three-dimensional integrated circuits; wafer-scale integration; PECVD process; Si; TSV; dielectric film deposition; dielectric stack engineering; passivation layers; plasma-enhanced chemical vapour deposition process; silicon wafers; size 300 mm; via-reveal passivation; wafer back side; Films; Passivation; Silicon; Silicon compounds; Temperature measurement; Tensile stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
  • Conference_Location
    Las Vegas, NV
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4799-0233-0
  • Type

    conf

  • DOI
    10.1109/ECTC.2013.6575631
  • Filename
    6575631
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=628439