DocumentCode :
628441
Title :
Impact of post-plating anneal and through-silicon via dimensions on Cu pumping
Author :
De Messemaeker, J. ; Pedreira, Olalla Varela ; Vandevelde, B. ; Philipsen, Harold ; De Wolf, Ingrid ; Beyne, Eric ; Croes, Kristof
Author_Institution :
Imec, Leuven, Belgium
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
586
Lastpage :
591
Abstract :
Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.
Keywords :
annealing; copper; electroplating; optical pumping; semiconductor device reliability; statistical analysis; three-dimensional integrated circuits; BEOL reliability; Cu; TSV dimension; high-temperature processing steps; irreversible extrusion; optical profilometry; optimal post-plating anneal impact condition; post-plating anneal temperature; pumping; reliability risk; statistical analysis; temperature 420 degC; through-silicon via dimension; Annealing; Finite element analysis; Reliability; Stress; Temperature; Temperature measurement; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575633
Filename :
6575633
Link To Document :
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