Title :
A more practical method of predicting flip chip solder bump electromigration reliability
Author :
Rao, Shiguo Richard
Author_Institution :
Vitesse Semicond. Corp., Camarillo, CA, USA
Abstract :
The study of flip chip solder bump electromigration reliability is mainly on daisy chain test structures on small test die that was subjected to high temperature and current density. Then an electromigration design rule is established based on the results on the test structures. However, for the big die flip chip BGA package, the actual electrical and thermal mechanical stress conditions of solder bumps are much more complicated and also vary with many factors such as the bump location, underfill properties and the shape of Cu traces on the package substrate, etc. These factors have significant effects on the bump failure mode and lifetime. Simply applying the design rule established on test structures may lead to a wrong or more optimistic reliability prediction. In this paper, a more practical method of predicting solder bump electromigration reliability was proposed by considering the major stress factors solder bumps will see in actual flip chip package in field application. The solder bump migration study was performed on a big die flip chip BGA package by considering the effects of temperature, thermal mechanical stresses for different bump location and pad structure and current crowding, etc. Multi level Finite Element Analysis (FEA) simulation was performed based on a multi physics electromigration model considering the current, temperature gradient, stress gradient and atomic density effects. The testing was performed on a super big flip chip BGA package by supplying different electrical currents to solder bumps. The migration induced bump failure was detected by electrical testing, non destructive 3D X-ray inspection and destructive cross-section analysis. The simulation results have a reasonably good correlation with the testing results. The predicted lifetime based on the new method shows more conservative and realistic result than the traditional electromigration design rule, particularly for bumps with high mechanical stresses and local current crowdi- g. Based on this study, some practical recommendations are also made to optimize the package design and material selection to improve the solder bump electromigration reliability.
Keywords :
ball grid arrays; electromigration; finite element analysis; flip-chip devices; integrated circuit design; integrated circuit packaging; integrated circuit reliability; solders; big die flip chip BGA package; bump failure mode; daisy chain test structures; destructive cross-section analysis; electrical testing; electromigration design rule; finite element analysis; flip chip package; flip chip solder bump electromigration reliability; major stress factors; multilevel FEA simulation; multiphysics electromigration model; nondestructive 3D X-ray inspection; small test die; solder bump migration study; Current density; Electromigration; Flip-chip devices; Materials; Mathematical model; Stress; Testing;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4799-0233-0
DOI :
10.1109/ECTC.2013.6575639