Title :
Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications
Author :
Ahmad, Mohiuddin ; Nagar, Mohan ; Weidong Xie ; Jimarez, M. ; Chang Gyun Ryu
Abstract :
With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently, it is important to place memories as close as possible to ASICs. Standard Printed Circuit Board (PCB) design rules make it difficult to place several memories very close to ASICs, and PCBs are already densely populated. Consequently, there are two prevailing technologies that are used to increase density: Through Silicon Vias (TSVs) or System-in-Package (SiP) modules. TSVs are still in early stages of development, whereas smaller SiP modules have already been used in Networking [1, 2]. In this study, we outline an innovative SiP module solution: Implementation of a very large (90 × 90 mm) SiP module with 14 packaged DDR3 memories and 1 large flip low K chip ASIC mounted on a common Ball Grid Array (BGA) substrate. This is likely the largest organic BGA module ever built. Finite Element Analysis was performed to estimate the optimal stiffener and lid parameters for minimal warpage. Complete substrates were assembled with key metrics measured at each step of the assembly process. Excellent coplanarity was achieved in the assembly process. The SiP modules were then mounted on PCBs and the board level assembly process characterized. The modules were successfully mounted on the PCBs. The procedures and key learnings from this evaluation will be outlined in this study.
Keywords :
Internet; application specific integrated circuits; assembling; ball grid arrays; electronics packaging; finite element analysis; mobile handsets; printed circuit design; random-access storage; system-in-package; three-dimensional integrated circuits; BGA module; DDR3 memories; Internet traffic; PCB design; SiP module; TSV; application specific processors; assembly process; ball grid array substrate; computers; data traffic requirements; finite element analysis; flip low K chip ASIC; memory devices; minimal warpage; mobile devices; networking applications; optimal stiffener; packaging solution; routers; standard printed circuit board design; tablets; through-silicon-via; ultra large system-in-package module; Aluminum; Assembly; Copper; Finite element analysis; Reliability; Substrates; BGA; Chip Package System Interaction; Chip Stacking; Chip-Memory Integration; Flip Chip BGA; Memories; Miniaturization; Reliability; SiP; System in Package; TSVs;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4799-0233-0
DOI :
10.1109/ECTC.2013.6575649