Damage pre-cursor based assessment of impact of high temperature storage on reliability of leadfree electronics

Electronic systems may be subjected to prolonged and intermittent periods of storage prior to deployment or usage. Prior studies have shown that leadfree solder interconnects show measurable degradation in the mechanical properties even after brief exposures to high temperature. In this paper, a method has been developed for the determining equivalent storage time to produce identical damage at a different temperature. Electronics subjected to accelerated tests often have a well-defined thermal profile for a specified period of time. Quantification of the thermal profile in field deployed electronics may be often difficult because of variance in the environment conditions and usage profile. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. Approach for mapping damage in leadfree second-level interconnects under between thermal conditions is new. High reliability applications such as avionics and missile systems may be often exposed to long periods of storage prior to deployment. Effect of storage at different temperature conditions can be mapped using the presented approach. A framework has been developed to investigate the system state and estimate the remaining useful life of solder ball subjected to a variety of isothermal aging conditions including 60°C, 75°C and 125°C for periods of time between 1-week and 4-week. Data on damage precursors has been collected and analyzed to derive physics based damage mapping relationships for aging. Mathematical relationships have been derived for the damage mapping to various thermal storage environments to facilitate determining appropriate time-temperature combination to reach a particular level of damage state. Activation energy for the leading indicators of failure is also computed. Specific damage proxies examined include the phase-growth indicator and the intermetallic thickness. The v- ability of the approach has been demonstrated for leadfree test assemblies subjected to multiple thermal aging at 60° C, 75°C and 125°C. Damage mapping relationships are derived from data based on the two separate leading indicators.