Title :
Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects
Author :
Karim, M.A. ; Franzon, Paul D. ; Kumar, Ajit
Author_Institution :
North Carolina State Univ., Raleigh, NC, USA
Abstract :
This paper compares the power efficiency of multiple 2D, 2.5D and 3D interconnect scenarios, specifically DDR3 with PCB, DDR3 with interposers, LPDDR2(3) with POP, wide I/Os with through-silicon vias (TSVs) and interposers and 32 nm technology CMOS drivers with TSVs and on-chip wires. It was found that DDR3 with PCB is the lowest power efficiency (15.65 mW/Gbps) and custom designed CMOS drivers optimized for the 2.5D and 3D give the highest power efficiency (0.23mW/Gbps). Optimization of a Back End of the Line (BEOL) 65 nm interposer interface is also presented for Wide IO interface to find maximize power efficiency. Power efficiency for different interposer trace lengths (5mm-40mm) and pitches (4.6μm-11.05μm) was analyzed. It was found that power efficiency decreases linearly with the increase of pitch and length of the interposer traces both in one stack and 4 stack die of Wide IO.
Keywords :
CMOS integrated circuits; interconnections; optimisation; three-dimensional integrated circuits; 2.5D interconnect solution; 2D interconnect solution; 3D interconnect solution; BEOL; CMOS driver; DDR3; LPDDR2; PCB; POP; TSV; interposer interconnection; optimization; power efficiency; power optimization; size 32 mm; size 4.6 mum to 11.05 mum; size 65 nm; stack die; through-silicon-vias; wide I/O; CMOS integrated circuits; Capacitors; Electrostatic discharges; Integrated circuit interconnections; Receivers; Simulation; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4799-0233-0
DOI :
10.1109/ECTC.2013.6575674
